View SONYCORPORATION-CXD2508AR_7199348.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the cxd2508aq/ar is a digital signal processor for cd players and is equipped with built-in digital filters, no-sound data detection circuit, and 1-bit dac. features dsp block digital pll efm frame sync protection sec strategy-based error correction subcode demodulation, crc checking digital spindle servo servo auto sequencer asymmetry compensation circuit digital audio interface output 16k ram double-speed playback capability new microcomputer interface circuit digital filter, dac block double-speed playback capability digital de-emphasis digital attenuation no-sound data detection circuit 4 fs oversampling filter secondary ? noise shaper pwm-system pulse conversion output recommended operating conditions supply voltage v dd note) 4.5 to 5.5v (double-speed playback) 3.5 to 5.5v (normal-speed playback) 3.4 to 5.5v (low power consumption or special playback mode) operating temperature topr ?0 (min.) 75 (max.) ? note) v dd (min.) is varied by the playback speed and built-in vco in the cxd2508aq/ar. 4.5v is the value using the vco which generates the slower frequency in double- speed playback. the table below shows the v dd (min.) for each condition. * when the internal operation of the lsi is set to double- speed mode and the crystal oscillation frequency is halved, normal-speed playback results. applications cd players structure silicon gate cmos ic absolute maximum ratings supply voltage v dd ?.3 to 7.0 v input voltage v i ?.3 to 7.0 v input voltage v in vss?.3v (min.) v dd +0.3 (max.) v output voltage v o ?.3 to 7.0 v storage temperature tstg ?0 to 125 ? supply voltage variation v ss ?v ss ?.3v (min.) +0.3v (max.) v dd ?v dd ?.3v (min.) +0.3v (max.) ?1 cxd2508aq/ar e94602a54-st cd digital signal processor sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxd2508aq 80 pin qfp (plastic) cxd2508aq 80 pin qfp (plastic) cxd2508ar 80 pin lqfp (plastic) cxd2508aq 80 pin qfp (plastic) playback speed vco high-speed vco normal-speed dac block 2 3.40 4.50 3.40 1 3.40 3.50 3.40 1 * 3.40 3.40 3.40 v dd (min.) [v]
?2 cxd2508aq/ar pin configuration wfck emphi emph dout c4m fstt mnt0 mnt1 mnt3 xrof c2po vss rfck gfs xpck xugf gtop bcki bck pcmdi pcmd lrcki lrck wdck scor sbso exck sqso sqck mute sens xrst data xlat clok vss sein cnin dato xlto clko spoa spob spoc xtsl xlon fok mon asye asyo asyi bias rf av dd 1 cltv avss1 v dd pco fili filo test lock mds mdp 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 16 17 18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19 20 21 22 23 24 1 zerol zeror dts1 v dd nlpwm lpwm av dd 2 av dd 3 xtai xtao avss3 avss2 nrpwm rpwm dts2 dts3 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 cxd2508aq emphi wfck zerol zeror dts1 v dd nlpwm lpwm av dd 2 av dd 3 xtai xtao avss3 avss2 nrpwm rpwm dts2 dts3 scor sbso emph dout c4m fstt mnt0 mnt1 mnt3 xrof c2po vss rfck gfs xpck xugf gtop bcki bck pcmdi pcmd lrcki exck sqso sqck mute sens xrst data xlat clok vss sein cnin dato xlto clko spoa spob spoc xtsl xlon 16 17 18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19 20 1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 63 64 61 62 cxd2508ar lrck wdck asye asyo asyi bias rf avdd1 cltv avss1 vdd pco fili filo test lock mds mdp mon fok 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33
?3 cxd2508aq/ar block diagram 2 3 4 5 6 7 9 10 11 13 14 15 16 17 18 19 22 23 24 25 26 27 29 30 40 39 38 37 36 34 31 41 42 43 44 45 46 47 48 49 50 51 52 54 55 56 57 58 59 60 70 69 63 64 65 66 61 62 73 74 77 78 1 sqck sqso exck sbso scor xlon spoa to c clok xlat data sens clko xlto dato xrof lock mds mdp mon dout nlpwm lpwm rpwm nrpwm fok sein cnin xpck filo fili pco cltv asyi asyo asye bias fstt c4m rf xtsl wfck emph gfs xugf gtop mnt0 mnt1 mnt3 c2po rfck emphi lrcki pcmdi bcki mute bck pcmd lrck wdck xtai xtao zerol zeror clock generator asymmetry corrector digital pll servo auto sequencer cpu interface sub code processor efm demodulator error corrector 16k ram digital clv digital out d/a interface digital filter + 1bit dac note) the pin numbers are for qfp. refer to the pin description for those of lqfp.
?4 cxd2508aq/ar pin description pin no. rq 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 scor sbso exck sqso sqck mute sens xrst data xlat clok v ss sein cnin dato xlto clko spoa spob spoc xtsl xlon fok mon mdp mds lock test filo fili pco v dd av ss 1 cltv o o i o i i o i i i i i i o o o i i i i o i o o o o i o i o i outputs a high signal when either subcode sync s0 or s1 is detected. sub p to w serial output. sbso readout clock input. sub q 80-bit serial output. sqso readout clock input. high: mute; low: release sens output to cpu. system reset. reset when low. serial data input from cpu. latch input from cpu. serial data is latched at the falling edge. serial data transfer clock input from cpu. gnd. sense input from ssp. track jump count signal input. serial data output to ssp. serial data latch output to ssp. latched at the falling edge. serial data transfer clock output to ssp. microcomputer extended interface (input a). microcomputer extended interface (input b). microcomputer extended interface (input c). crystal selection input. low for 16.9344mhz; high for 33.8688mhz microcomputer extended interface (output). focus ok input. used for sens output and the servo auto sequencer. spindle motor on/off control output. spindle motor servo control. spindle motor servo control. gfs is sampled at 460hz; when gfs is high, this pin outputs a high signal. if gfs is low eight consecutive samples, this pin outputs low. test pin. normally gnd. master pll (slave = digital pll) filter output. master pll filter input. master pll charge pump output. digital power supply for dsp. analog gnd for dsp. master pll vco control voltage input. symbol i/o description
?5 cxd2508aq/ar pin no. rq 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 av dd1 rf bias asyi asyo asye wdck lrck lrcki pcmd pcmdi bck bcki gtop xugf xpck gfs rfck v ss c2po xrof mnt3 mnt1 mnt0 fstt c4m dout emph emphi wfck zerol zeror dts1 v dd i i i o i o o i o i o i o o o o o o o o o o o o o o i o o o i analog power supply for dsp. efm signal input. constant current input of asymmetry compensation circuit. comparator voltage input of asymmetry compensation circuit. efm full-swing output (low = vss, high = v dd ). low: asymmetry compensation off; high: asymmetry compensation on. d/a interface for 48-bit slot. word clock (2fs). d/a interface for 48-bit slot. lr clock (fs). lr clock input for dac. (48-bit slot) d/a interface. serial data (two's complement, msb first). audio data input for dac. (48-bit slot) d/a interface. bit clock. bit clock input for dac. (48-bit slot) gtop output. xugf output. xplck output. gfs output. rfck output. gnd. c2po output. xraof output. mnt3 output. mnt1 output. mnt0 output. 2/3 frequency-divider output for pins 73 and 74. 4.2336mhz output. digital out output. outputs high signal when the playback disc has emphasis, low signal when no emphasis. dac de-emphasis on/off. high: on; low: off. wfck (write frame clock) output. no-sound data detection output; high when no sound data is detected. (left channel) no-sound data detection output; high when no sound data is detected. (right channel) test pin 1 for dac; normally low. digital power supply for dac. symbol i/o description
?6 cxd2508aq/ar note) pcmd is an msb first, two's complement output. gtop is used to monitor the frame sync protection status. (high: sync protection window released.) xugf is the negative pulse for the frame sync derived from the efm signal. it is the signal before sync protection. xplck is the inverse of the efm pll clock. the pll is designed so that the falling edge of xplck and the efm signal transition point coincide. gfs goes high when the frame sync and the insertion protection timing match. rfck is derived with the crystal accuracy. this signal has a cycle of 136. c2po represents the data error status. xraof is generated when the 16k ram exceeds the 4f jitter margin. pin no. rq 67 68 69 70 71 72 73 74 75 76 77 78 69 70 71 72 73 74 75 76 77 78 79 80 nlpwm lpwm av dd 2 av dd 3 xtai xtao av ss 3 av ss 2 nrpwm rpwm dts2 dts3 o o i o o o i i left channel pwm output. (reverse phase) left channel pwm output. (forward phase) power supply for pwm driver. power supply for crystal. 33.8688mhz crystal oscillation circuit input. 33.8688mhz crystal oscillation circuit output. gnd for crystal. gnd for pwm driver. right channel pwm output. (reverse phase) right channel pwm output. (forward phase) dac test pin 2; normally low. dac test pin 3; normally low. symbol i/o description
?7 cxd2508aq/ar electrical characteristics dc characteristics (v dd = av dd = 5.0v 5%, v ss = av ss = 0v, topr = ?0 to +75?) note) input voltage (1) input voltage (2) input voltage (3) output voltage (1) output voltage (2) output voltage (3) output voltage (4) item high level input voltage low level input voltage high level input voltage low level input voltage high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage input leak current tri-state pin output leak current input voltage v ih (1) 0.7v dd 0.3v dd 0.2v dd v dd 0.4 v dd 0.4 v dd 0.4 v dd 0.4 ? ? v dd v il (1) v ih (2) v il (2) v ss 0.8v dd v dd ?.8 0 v dd ?.8 0 v dd ?.5 0 v dd ?.4 0 v oh (1) v ol (1) v oh (2) v ol (2) v oh (3) v ol (3) v oh (4) v ol (4) i li i lo v in (3) v v v v v v v v v v v v ? ? v * 1 * 2 * 4 * 5 * 6 * 7 * 1 , * 2 , * 3 * 8 * 3 i oh = ?ma i ol = 4ma i oh = ?ma i ol = 4ma i oh = ?.28ma i ol = 0.36ma i oh = ?0ma i ol = 10ma v i = 0 to 5.25v v o = 0 to 5.25v analog input schmitt input conditions min. typ. max. unit applicable pins applicable pins * 1 xtsl, data, xlat, pcmdi, emphi, dts1, dts2, dts3, spoa, spob, spoc * 2 clok, xrst, exck, sqck, mute, fok, sein, cnin, asye, lrcki, bcki * 3 cltv, fili, rf, bias, asyi * 4 mdp, pco * 5 asyo, dout, fstt, c4m, sbso, sqso, scor, emph, mon, lock, wdck, dato, clko, xlto, sens, mds, lrck, wfck, pcmd, bck, gtop, xugf, xpck, gfs, rfck, xrof, mnt0, mnt1, mnt3, zerol, zeror * 6 filo * 7 lpwm, nlpwm, rpwm, nrpwm * 8 sens, mds, mdp note) "av dd " refers to av dd 1, av dd 2, and av dd 3. in addition, "avss" refers to avss1, avss2, and avss3.
?8 cxd2508aq/ar ac characteristics 1) xtai pin (1) when using self-oscillation (topr = ?0 to +75?, v dd = av dd = 5.0v 5%) (2) when inputting pulses to xtai (topr = ?0 to +75?, v dd = av dd = 5.0v 5%) (3) when inputting sine waves to xtai via a capacitor (topr = ?0 to +75?, v dd = av dd = 5.0v 5%) oscillation frequency f max 15 34 mhz item symbol min. typ. max. unit high level pulse width low level pulse width pulse cycle input high level input low level rise time, fall time t whx 13 500 ns t wlx 13 500 ns t ck 26 1,000 ns v ihx v dd ?1.0 v v ilx 0.8 v t r , t f 10 ns item symbol min. typ. max. unit input amplitude v 1 2.0 v dd + 0.3 vp-p item symbol min. typ. max. unit tr tr t whx t wlx t cx v ilx v ihx 0.1 v ihx 0.9 v ihx xtai v dd /2
?9 cxd2508aq/ar 2) clok, data, xlat, cnin, sqck exck pins (v dd = av dd = 5.0v 5%, v ss = av ss = 0v, topr = ?0 to +75?) clock frequency clock pulse width setup time hold time delay time latch pulse width exck sqck frequency exck sqck pulse width f ck t wck t su t h t d t wl f t f wt 750 300 300 300 750 750 * 0.65 0.65 * mhz ns ns ns ns ns mhz ns item symbol min. typ. max. unit t wck t wck 1/f cx t h t su t wl t d 1/f r t wt t wt t h t su clk data xlt exck cnin sqck subq sqck bck pulse width datal, r setup time datal, r hold time lrck setup time t w t su t h t su 118 141 nsec nsec nsec nsec item symbol conditions typ. 94 18 18 18 min. max. unit v dd /2 v dd /2 t w (bcki) t w (bcki) t su (pcmdi) t h (pcmdi) t su (lrcki) bcki pcmdi lrcki * in pseudo double-speed playback mode, when sl0 = sl1 = 1, the maximum operating frequency for sqck is 300khz and the minimum pulse width is 1.5s. 3) bcki, lrcki, and pcmdi pins (v dd = av dd = 5.0v 5%, v ss = av ss = 0v, topr = ?0 to +75?)
?10 cxd2508aq/ar 1-bit dac block analog characteristics (v dd = av dd = 5.0v, v ss = av ss = 0v, ta = 25?) for both items, fs=44.1khz the circuits for measuring the total harmonic distortion and s/n ratio are shown below. analog lpf circuit block diagram for measuring analog characteristics item total harmonic distortion s/n ratio symbol thd s/n conditions 1khz, 0db data playback mode 1khz, 0db data (using filter a) normal speed pseudo double-speed playback normal speed pseudo double-speed playback 87 83 0.015 0.025 min. typ. max. unit % db audio analyzer 100 330k 22 2700p 560p shibasoku (am51a) 4.7k 4.7k 4.7k 820p 4.7k 4.7k 4.7k 820p 470p 470p 11k 11k rpwm nrpwm rf 768fs/384fs (normal speed/pseudo double-speed playback) cxd2508aq/ar rpwm nrpwm nlpwm lpwm rch a lch b shibasoku (am51a) audio analyzer analog circuit efm signal generater
?11 cxd2508aq/ar description of functions 1. cpu interface and instructions cpu interface this interface uses data, clok, and xlat to set the modes. the interface timing chart is shown below. information on each address and the data is provided in table 1-1. the internal registers are initialized by a reset when xrst = 0; the initialization data is shown in table 1-2. note) when xlat is low, exck and sqck must be set high. 750ns or more d1 data address d2 d3 d0 d1 d2 d3 750ns or more 300ns max valid clok data xlat registers 4 to e
?12 cxd2508aq/ar register name 4 auto sequence blind (a, e), overflow (c) brake (b) kick (d) auto sequence (n) track jump count setting mode specification function specification audio ctrl serial bus ctrl servo coefficient setting clv ctrl clv mode test mode 0 0 1 1 1 1 1 1 1 1 command address data 1 vco sel fstt sel d3 d2 as3 as2 as1 as0 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 2 data 3 data 4 5 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 1 0 2048 0 1024 0 dads 512 256 128 ad6 64 ad5 32 ad4 16 ad3 8 ad2 4 ad1 2 ad0 1 7 6 8 9 a b c d e f dclv pwmmod gain mdp1 0.18ms 0.09ms 0.05ms 0.02ms 0.36ms 0.18ms 0.09ms 0.05ms 11.6ms 5.8ms 2.9ms 1.45ms 32768 16384 8192 4096 cd- rom wsel 0 0 0 0 0 mute att sl 1 sl 0 cpusr 0 tb tp cm3 cm2 cm1 cm0 gain mdp0 gain mds1 gain mds0 clvs gain dout mute dout on/off dspb on/off don't use command table table 1-1
?13 cxd2508aq/ar 4 auto sequence blind (a, e), overflow (c) brake (b) kick (d) auto sequence (n) track jump count setting mode specification function specification audio ctrl serial bus ctrl servo coefficient setting clv ctrl clv mode test mode 0 0 1 1 1 1 1 1 1 1 command address data 1 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 data 2 data 3 data 4 5 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 7 6 8 9 a b c d e f don't use reset initialization table 1-2 register name
?14 cxd2508aq/ar 1-1. the meaning of the data for each address is explained below. $4x commands rxf = 0 forward rxf = 0 reverse when the focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. when the track jump/move commands ($48 to $4f) are canceled, $25 is sent and the auto sequence is interrupted. $5x commands auto sequence timer setting setting timers: a, e, c, b ex.) d2 = d0 = 1, d3 = d1 = 0 (initial reset) a = e = c = 0.11ms b = 0.23ms $6x commands auto sequence timer setting setting timer: d ex.) d3 = 0, d2 = d1 = d0 = 1 (initial reset) d = 10.15ms $7x commands auto sequence track jump/move count setting (n) this command is used to set n when a 2n track jump and an n track move are executed for auto sequence. the maximum track count is 65,535, but note that with 2n track jumps the maximum track jump count is determined by the mechanical limitations of the optical system. the number of track jump is counted according to the signals input from cnin pin. cancel focus-on 1 track jump 10 track jump 2n track jump n track move 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 rxf rxf rxf rxf command as3 as2 as1 as0 blind (a, e), over flow (c) brake (b) 0.18ms 0.36ms 0.09ms 0.18ms 0.05ms 0.09ms 0.02ms 0.05ms command d3 d2 d1 d0 kick (d) 11.6ms 5.8ms 2.9ms 1.45ms command command data 1 data 2 data 3 data 4 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 d0 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 auto sequence track jump number setting d3 d2 d1 d0
?15 cxd2508aq/ar command data 1 mode specification cdrom dout mute dout on-off wsel d3 d2 d1 d0 data 2 000 vco sel d3 d2 d1 d0 command bit c2po timing cdrom = 1 cdrom = 0 1-3 1-3 cdrom mode; average value interpolation and pre-value hold are not performed. audio mode; average value interpolation and pre-value hold are performed. processing command bit dout mute = 1 dout mute = 0 digital out output is muted. (da output is not muted.) when no other mute conditions are set, digital out output is not muted. processing command bit dout on-off = 1 dout on-off = 0 digital out is output from the dout pin. digital out is not output from the dout pin. processing command bit sync protection window width wsel = 1 wsel = 0 26 channel clock * 6 channel clock anti-rolling is enhanced. sync window protection is enhanced. application command bit processing vcosel = 1 vcosel = 0 vco for double-speed playback is selected. vco for normal-speed playback is selected. double-speed playback or low voltage operation is possible. the selection is made for the normal speed playback. application command data 1 function specifications 0 dspb on-off 00 d3 d2 d1 d0 data 2 000 fstt sel d3 d2 d1 d0 command bit dspb = 0 dspb = 1 normal-speed playback double-speed playback processing command bit fsttsel = 0 fsttsel = 1 the clock with two-thirds frequency of crystal is output to fstt pin. the clock with the sixth frequency of crystal is output to fstt pin. $8x commands * in normal-speed playback, channel clock = 4.3218mhz. $9x commands
?16 cxd2508aq/ar the attenuation data consists of seven bits (ad6 to ac0), and 127 settings are possible. audio output from 01 (h) to 7e (h) is determined according to the following formula: audio output = 20 log ( ) db ex.) when the attenuation data is 7a (h) audio output=20 log ( ) db = ?.417db soft mute with soft mute function, when the attenuation data goes from 7f (h) (0db) to 00 (h) ( ) or vice versa, muting is turned on/off with a muting time of 1024/fs [s] = 23.2 [ms] (fs = 44.1khz). command data 1 audio ctrl 0 0 mute att d3 d2 d1 d0 data 2 dads d3 d2 d1 d0 command bit mute = 0 mute = 1 mute off. mute on. 0 data is output from dsp. meaning command bit att = 0 att = 1 attenuation off. ?2db meaning command bit dads = 0 dads = 1 normal-speed playback for dac block double-speed playback for dac block processing command command bit ad6 to ad0 7f (h) 7e (h) to 01 (h) 00 (h) audio output 0db ?.13db to ?2.144db data 3 audio ctrl ad6 ad5 ad4 d2 d1 d0 data 4 ad3 ad2 ad1 ad0 d3 d2 d1 d0 attenuation data 128 122 128 $ax commands in the case of using the crystal of 768fs (fs = 44.1khz) digital attenuation the audio output level from dac can be attenuated by setting ad6 to ac0 of register a. (with a built-in primary noise shaper)
?17 cxd2508aq/ar 0db 7f (h) a y1 b y3 y2 c 23.2 [ms] 00(h) serial bus ctrl sl1 sl0 cpusr 0 command d3 d2 d1 d0 command bits sl1 0 0 1 1 sl0 0 1 0 1 same interface mode as the cdl40 series. sbso is output from sqso pin. in other words, subcodes p to w are read out from sqso. input the readout clock to sqck. sens is output from sqso pin. each output signal is output from sqso pin. input the readout clock to sqck. (see the timing chart 1-2.) processing command bits cpusr = 1 cpusr = 0 xlon pin is high. xlon pin is low. processing attenuation operation assume attenuation data x1, x2, and x3, where x1 > x3 > x2, and audio output y1, y2, and y3, where y1 > y3 > y2. first, assume x1 is transferred and then x2 is transferred. if x2 is transferred before y1 is reached (state "a" in the diagram), then the value continues approaching y2. next, if x3 is transferred before y2 is reached (either state "b" or "c" in the diagram), the value begins approaching y3 from the current value at that point. $bx commands this command switches the method of interfacing with the cpu. with the cdl500 series, the number of signal lines between the cpu and the dsp can be reduced in comparison with the cdl40 series. also, the error rate can be measured with the cpu.
?18 cxd2508aq/ar $cx commands clvs mode gain setting: gclvs clvp mode gain setting: gmdp, gmds servo coefficient setting clv ctrl ($dx) gain mdp1 gain mdp0 gain mds1 gain mds0 gain clvs gain mds1 0 0 0 0 1 1 gain mds0 0 0 1 1 0 0 gain clvs 0 1 0 1 0 1 gclvs ?2db ?db ?db 0db 0db +6db command d3 d2 d1 d0 gain mdp1 0 0 1 gain mdp0 0 1 0 gmdp ?db 0db +6db gain mds1 0 0 1 gain mds0 0 1 0 gmds ?db 0db +6db
?19 cxd2508aq/ar clv ctrl dclv pwm md tb tp clvs gain command d3 d2 d1 d0 clv mode cm3 cm3 0 1 1 1 1 0 cm2 0 0 0 1 1 1 cm1 0 0 1 1 1 1 cm0 0 0 0 0 1 0 mode stop kick brake clvs clvp clva explanation see the timing chart 1-4. see the timing chart 1-5. see the timing chart 1-6. cm2 cm1 cm10 command d3 d2 d1 d0 command bit dclv pwm md = 1 dclv pwm md = 0 clv pwm mode specified. both mds and mdp are used. clv pwm mode specified. ternary mdp values are output. explanation (see the timing chart 1-3.) command bit tb = 0 tb = 1 tp = 0 tp = 1 bottom hold in clvs mode at cycle of rfck/32 bottom hold in clvs mode at cycle of rfck/16 peak hold in clvs mode at cycle of rfck/4 peak hold in clvs mode at cycle of rfck/2 explanation $dx commands see the $cx command. $ex commands stop : spindle motor stop mode kick : spindle motor forward rotation mode brake : spindle motor reverse rotation mode clvs : rough servo mode. when rf-pll circuit lock is disengaged, this mode is used to pull the disc rotations within the rf-pll capture range. clvp : pll servo mode. clva : automatic clvs/clvp switching mode. this mode is normally used during playback.
?20 cxd2508aq/ar timing chart 1-1 rch 16bit c1 pointer rch 16bit c2 pointer if c2 pointer = 1, data is ng c2 pointer for upper 8bits c2 pointer for lower 8bits rch c2 pointer c2 pointer for upper 8bits c2 pointer for lower 8bits lch c2 pointer lrck wdck cdrom = 0 c2p0 cdrom = 1 c2p0
?21 cxd2508aq/ar timing chart 1-2 c1f1 0 1 1 c1f2 0 0 1 c1 correction status no error single error correction irretrievable error c2f1 0 1 1 c2f2 0 0 1 c2 correction status no error single error correction irretrievable error $bc latch set sqck and exck high during this interval. internal signal latch 750ns or more (1500ns or more in low power consumption mode) spoa spob spoc xtsl wfck scor gfs gtop emph fok lock rfck xraof c1f1 c1f2 c2f1 c2f2 xlat sqck sqso
?22 cxd2508aq/ar timing chart 1-3 timing chart 1-4 mds mdp dclv pwm md = 0 z acceleration 132khz 7.6s n ?236 (ns) n = 0 to 31 deceleration z dclv pwm md = 0 mds mdp 7.6s acceleration n ?236 (ns) n = 0 to 31 deceleration dclv pwm md = 0 mds mdp mon stop z z l dclv pwm md = 1 mds mdp mon stop l l
?23 cxd2508aq/ar timing chart 1-5 dclv pwm md = 0 mds mdp mon kick z z h 7.6s h kick dclv pwm md = 1 mds mdp mon h h h l
?24 cxd2508aq/ar timing chart 1-6 dclv pwm md = 0 mds mdp mon brake z z h h dclv pwm md = 1 mds mdp mon h
?25 cxd2508aq/ar 1-2. description of sens output the following signals are output from sens, depending on the microcomputer serial register value (latching not required). note that the sens output can be read from sqso pin when sl1 = 1 and sl0 = 0. (see the $bx commands.) 2. subcode interface this section explains the subcode interface. there are two methods for reading out a subcode externally. the 8-bit subcodes p to w can be read from sbso by inputting exck to the cxd2508aq/ar. sub q can be read out after the crc check of the 80 bits data in the subcode frame. this accomplished, after checking scor and crcf, by inputting 80 clock pulses to sqck and reading data from sqso pin. 2-1. p to w subcode read data can be read out by inputting exck immediately after wfck falls. (see fig. 2-1.) also, sbso can be read out from sqso pin when sl1 = 0 and sl0 = 1. (see the $bx commands.) 2-2. 80-bit sub q read fig. 2-2 shows the peripheral block of the 80-bit sub q register. first, sub q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the crc check circuit. 96-bit sub q is input, and if the crc is ok, it is output to sqso with crcf = 1. in addition, the 80 bits are loaded into the parallel/serial register. when sqso goes high 400s or more later (monostable multivibrator time constant) after the subcode is read out, the cpu determines that new data (which passed the crc check) has been loaded. in the cxd2508aq/ar, when 80-bit data is loaded, the order of the msb and lsb is inverted for each byte. as a result, although the sequence of bytes is the same, the bits within the bytes are now ordered lsb first. once the fact that the 80-bit data has been loaded is confirmed, sqck is input so that the data can be read. in the cxd2508aq/ar, the sqck input is detected, and when it is low the retriggerable monostable multivibrator is reset. the retriggerable monostable multivibrator has a time constant from 270 to 400s. when the duration of sqck is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the s/p register is not loaded into the p/s register. while the monostable multivibrator is being reset, data can not be loaded in the 80-bit parallel/serial register. in other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant, the register will not be rewritten by crcok and others. fig. 2-3 shows timing chart. although a clock is input from sqck pin to actually perform these operations, the high and low intervals for this clock should be between 750ns and 120s. sein, a signal input to the this ic from the ssp, is output. low while the auto sequencer is in operation, high when operation terminates. outputs the signal input to the fok pin. normally, fok (from rf) is input. high for "focus ok". sein, a signal input to this ic from the ssp, is output. high when the played back frame sync is obtained with the correct timing. low when the efm signal, after passing through the sync detection filter, is lengthened by 64 channel clock pulses or more. sens pin is fixed low. sein xbusy fok sein gfs ov64 "l" $0x, 1x, 2x, 3x $4x $5x $6x $ax $ex $7x, 8x, 9x, bx, cx, dx, fx microcomputer serial register value (latching not required) sens output meaning
?26 cxd2508aq/ar timing chart 2-1 interrel pll clock 4.3218 d mhz wfck scor exck sbso 400ns max s0 ?s1 q r wfck scor exck sbso s0?1 q r s t u v w s0?1 p1 q r s t u v w p1 p2 p3 same same subcode p.q.r.s.t.u.v.w read timing
?27 cxd2508aq/ar block diagram 2-2 subq sin a b c d e f g h (afram) h g f e d c b a (asec) (amin) 80bit s/p register addrs ctrl 8 8 8 order inversion 8 8 8 8 8 8 si ld ld ld ld ld ld ld ld 80bit s/p register so shift sqck crcf mix sqso mono/multi crcc subq shift
?28 cxd2508aq/ar timing chart 2-3 1 2 3 91 92 93 94 95 96 97 98 wfck scor sqso sqck mono/multi (interral) order inversion crcf1 determined by mode l crcf2 80 clock registere load forbidder 270 to 400s for sqck = high 750ns to 120s 300ns max crcf adr0 adr1 adr2 adr3 ctl0 ctl1 ctl2 ctl3 sqck sqso 1 2 3
?29 cxd2508aq/ar 3. description of other functions 3-1. channel clock regeneration by digital pll circuit the channel clock is necessary for demodulating the efm signal regenerated by the optical system. assuming t as the channel clock cycle, the efm signal is demodulated in an integer multiple of t from 3t to 11t. in order to read the information in the efm signal, this integer value must be read correctly. as a result, t, that is channel clock, is required. in an actual player, the fluctuation in the spindle rotation alters the width of the efm signal pulses, making a pll necessary for regenerating channel clock. the block diagram of this pll is shown in fig. 3-1. the cxd2508aq/ar has a built-in two-stage pll as shown in the diagram. the first-stage pll generates a high-frequency clock needed by the second-stage digital pll. the second-stage pll is a digital pll that regenerates the actual channel clock, and has a 250khz (normal state) or more capture range. block diagram 3-1 x'tal osc i/m i/n phase comparator pco fili filo cltv v dd vco rfpll digital pll
?30 cxd2508aq/ar 3-2. frame sync protection in a cd player operating at normal speed, a frame sync is recorded approximately every 136s (7.35khz). this signal is used as a reference to know which data is the data within a frame. conversely, if the frame sync can not be recognized, the data is processed as error data because it can not be recognized what the data is. as a result, recognizing the frame sync properly is extremely important for improving playability. in the cxd2508aq/ar, window protection and forward protection/backward protection have been adopted for frame sync protection. the adoption of these functions achieves very powerful frame sync protection. there are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (wsel = 0/1). in addition, the forward protection counter is fixed to 13, and the backward protection counter is fixed to 3. in other words, when the frame sync is being played back normally and then can not be detected due to scratches, a maximum of 13 frames are inserted. if frame sync can not be detected for 13 frames or more, the window is released and the frame sync is resynchronized. in addition, immediately after the window is released and resynchronization is executed, if a proper frame sync can not be detected within 3 frames, the window is released immediately. 3-3. error correction in the cd format, one 8-bit data contains two error correction codes, c1 and c2. for c1 correction, the code is created with 28-byte information and 4-byte c1 parity. for c2 correction, the code is created with 24-byte information and 4-byte parity. both c1 and c2 are reed-solomon codes with a minimum distance of 5. the cxd2508aq/ar sec strategy provides excellent playability through powerful frame sync protection and c1 and c2 error corrections. the correction status can be monitored outside the lsi. see table 3-1. when the c2 pointer is high, the data in question was uncorrectable. either the pre-value was held for that data, or an average value interpolation was made. mnt3 0 0 0 1 1 1 mnt1 0 0 1 0 0 1 mnt0 0 1 1 0 1 1 description no c1 errors one c1 errors corrected c1 correction impossible no c2 errors one c2 errors corrected c2 correction impossible table 3-1.
?31 cxd2508aq/ar timing chart 3-2 3-4. da interface the cxd2508aq/ar da interface is as described below. this interface includes 48 cycles of the bit clock within one lrck cycle, and is msb first. when lrck is high, the data is for the left channel. normal-speed pb 400 to 500ns rfck mnt3 mnt1 mnt0 t = dependent on error condition c1 correction c2 correction strobe strobe c4m mnto, 1, 3 valid valid invalid
?32 cxd2508aq/ar timing chart 3-3 lrck (44.1k) bck (2.12m) wdck pcmd lrck (88.2k) bck (4.23m) wdck pcmd 48bit slot normal-speed playback 1 24 ro lch msb (15) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rmsb ro lch msb (15) 24 rch msb 23456789101112 48bit slot double-speed playback 12 lo
?33 cxd2508aq/ar 3-5. digital out there are three digital out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. the cxd2508aq/ar supports type 2 form 1. sub q data which are matched twice in succession after a crc check are input to the first four bits (bit 0 to 3) of channel status. table 3-2. 3-6. servo auto sequencer this function performs a series of controls, including auto focus and track jumps. when the auto sequence command is received from the cpu, auto focus, 1 track jump, 2n track jumps, and n track move are executed automatically. ssp (servo signal processor lsi) is used in an exclusive manner during the auto sequence execution (when xbusy = low), so that commands from the cpu are not transferred to the ssp, but they can be sent to the cxd2508aq/ar. connect the cpu, rf and ssp as shown in fig. 3-4. when clok goes from low to high while xbusy is low, xbusy does not become high for a maximum of 100s after that point. this is designed to prevent the transfer of erroneous data to the ssp when xbusy changes from low to high by the monostable multivibrator, which is reset by clok being low (when xbusy is low). 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 id0 id1 copy emph 0 0 0 0 1 0 0 0 0 0 0 0 from sub q 0 16 32 48 176 bit0 to 3 ?sub q control bits that matched twice with crcok digital out c bit 12 34 56 78 9101112131415
?34 cxd2508aq/ar (a) auto focus ($47) focus search up is performed, fok and fzc are checked, and the focus servo is turned on. if $47 is received from the cpu, the focus servo is turned on according to fig. 3-5. the auto focus starts with focus search up, and the pickup should be lowered beforehand (focus search down). in addition, blind e of register 5 is used to eliminate fzc chattering. in other words, the focus servo is turned on at the falling edge of fzc after fzc has been continuously high for a longer time than e. connection diagram for using auto sequencer (example) rf fok ssp c. out sens data clk xlt cnin fok data clok xlat sens micro-computer cxd2508a sein dato clko xlto auto focus focus search up fok = h no yes fzc = h no yes fzc = l no yes end focus servo on (checks whether fzc is continuously high or not for the period of time e set in register 5) fig. 3-4. fig. 3-5-(a). auto focus flow chart
?35 cxd2508aq/ar fig. 3-5-(b). auto focus timing chart (b) track jump 1, 10, and 2n-track jumps are performed respectively. always use this when focus, tracking, and the sled servo are on. note that tracking gain up and braking on ($17) should be sent beforehand because they are not performed. 1-track jump when $48 ($49 for rev) is received from the cpu, an fwd (rev) 1-track jump is performed in accordance with fig. 3-6. set blind a and brake b with register 5. 10-track jump when $4a ($4b for rev) is received from the cpu, an fwd (rev) 10-track jump is performed in accordance with fig. 3-7. the principal difference between the 10-track jump and the 1-track jump is whether to kick the sled or not. in addition, after kicking the actuator, 5 tracks have been counted through cnin, and the brake is applied to the actuator. then, the actuator speed is found to have slowed up enough (determined by the cnin cycle becoming longer than the overflow c set in register 5), and the tracking and sled servos are turned on. 2n-track jump when $4c ($4d for rev) is received from the cpu, an fwd (rev) 2n-track jump is performed in accordance with fig. 3-8. the track jump count "n" is set in register 7. although n can be set to 2 16 tracks, note that the setting is actually limited by the actuator. cnin is used for counting the number of jumps. although the 2n-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "d", set in register 6. n-track move when $4e ($4f for rev) is received from the cpu, an fwd (rev) n-track move is performed in accordance with fig. 3-9. n can be set to a maximum of 2 16 tracks. cnin is used for counting the number of jumps. this n-track move uses a method in which only the sled is moved, and is suited for moves over thousands of tracks. xlt fok sein (fzc) busy command for ssp $47latch $03 blind e $08
?36 cxd2508aq/ar fig. 3-6-(a). 1-track jump flow chart track no yes end track kick sled servo wait (blind a) cnin = track rev kick wait (brake b) track sled servo on (fwd kick for rev jump) (rev kick for rev jump) fig. 3-6-(b). 1-track jump timing chart xlt cnin busy command for ssp $48 (rev = $49) latch $28 ($2c) blind a brake b $2c ($28) $25
?37 cxd2508aq/ar fig. 3-7-(a). 10-track jump flow chart 10 track no yes end track, sled fwd kick wait (blind a) cnin=5 ? track, rev kick track sled servo on (checks whether the cnin cycle is longer than overflow c) (counts cnin 5) no yes c = overflow ? fig. 3-7-(b). 10-track jump timing chart xlt cnin busy command for ssp $4a (rev = $4b) latch blind a $2a ($2f) cnin 5count $2e ($2b) overflow c $25
?38 cxd2508aq/ar fig. 3-8-(a). 2n-track jump flow chart 2n track no yes end track, sled fwd kick wait (blind a) cnin = n track rev kick track servo on no yes c = overflow wait (kick d) sled servo on fig. 3-8-(b). 2n-track jump timing chart xlt cnin busy command for ssp blind a $2a ($2f) cnin n count $2e ($2b) overflow kick d $26 ($27) $25 $4c (rev = $4d) latch
?39 cxd2508aq/ar fig. 3-9-(a). n-track move flow chart n track move no yes end track servo off sled fwd kick wait (blind a) cnin = n end track, sled servo on fig. 3-9-(b). n-track move timing chart xlt cnin busy command for ssp $22 ($23) blind a cnin n count $25 $4e (rev = $4f) latch
?40 cxd2508aq/ar 3-7. digital clv fig. 3-10 shows the block diagram. digital clv makes pwm output in clvs and clvp with the mds error and mdp error signal sampling frequency increased to 130khz during normal-speed operation. in addition, the digital spindle servo can set the gain. digital clv clvs u/d gain mds error mdp error clvs p/s 0, ?db measure measure 2/1 mux over sampling filter-1 gs (gain) gp (gain) clv p clv s 1/2 mux clv-p/s over sampling filter-2 noise shape modulation kick, brake stop dclvmd mdp mds mode select fig. 3-10. block diagram
?41 cxd2508aq/ar 3-8. asymmetry compensation fig. 3-11 shows the block diagram and circuit example. fig. 3-11. example of asymmetry compensation application circuit asye rf r1 r1 asyo asyi r2 2 r1 5 = bias r1 r1 r2 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?42 cxd2508aq/ar 3-9. setting method of the cxd2508aq/ar playback speed (a) signal processing block (dsp block) the playback mode shown below can be selected by the combination of crystal, xtsl pin and double- speed command (dspb) in the cxd2508aq/ar. fs = 44.1khz * 1 low power consumption mode. the processing speed is halved in the lsi so that the power consumption can be decreased. (b) dac block the operating speed at dac block is determined by the crystal and the double-speed command dads in dac block in spite of the operating conditions of dsp block mentioned above. then, the playback mode for dac block and dsp block can be determined independently. (for example, normal-speed playback for dsp block; low power consumption playback for dac block.) the dac block supports the normal speed and double speed. * dads is controlled by sending the command to dsp block. * 2 low power consumption mode. the processing speed is halved in the lsi so that the power consumption can be decreased. playback mode at dsp block mode 1 2 3 4 5 * 1 crystal 768fs 768fs 384fs 384fs 384fs xtsl 1 1 0 0 1 dspb 0 1 0 1 1 speed at dsp block 1 2 1 2 1 playback mode at dac block mode 1 2 3 * 2 crystal 768fs 768fs 384fs dads 0 1 1 speed at dac block 1 2 1
?43 cxd2508aq/ar lpwm (rpwm) 5 4 3 ? ? ? ? ? 33.8688 [mhz] (768fs) ? ? ? ? ? ? ? ? ? 3 4 5 1.4112 [mhz] (32fs) nlpwm (nrpwm) noise shaper output value ? ? ? lpwm (prwm) 4 2 0 ? ? 2.8224 [mhz] (64fs) ? ? 0 2 4 33.8688 [mhz] (768fs) lpwm (rpwm) 4 2 0 ? ? 1.4112 [mhz] (32fs) ? ? 0 2 4 16.9344 [mhz] (384fs) 4. 1-bit dac block 4-1. pwm output pattern in the cxd2508aq/ar, pwm outputs from the dac include forward phase pwm (rpwm, lpwm) and inverted pwm (nrpwm, nlpwm). by determining the difference between these pwm outputs in the subsequent analog lpf, the noise and others can be canceled in the digital block. in addition, this method also yields improvements in the analog characteristics. the pwm output waveforms differ for each of the cxd2508aq/ar three playback modes (normal, double- speed, and pseudo double-speed). (in the following explanation, fs = 44.1khz.) during normal speed playback (dspb = 0, crystal = 768fs), eleven values (integers from ? to 5) are taken within the 32fs cycle. the minimum pulse width is ?, and the maximum pulse width is +5. the minimum variation width of change for pwm is the 384 fs cycle. (see fig. 4-3.) fig. 4-1. in double-speed playback (dspb = 1, crystal = 768fs), five values (?, ?, 0, 2, 4) are taken within the 64fs cycle. (see fig. 4-4.) fig. 4-2. in pseudo double-speed playback (dspb = 1, crystal = 384fs), five values (?, ?, 0, 2, 4) are taken within the 32fs cycle. (see fig. 4-5.) fig. 4-3. 4-2. input timing for dac block fig. 4-4 shows the input timing for dac section. in the cxd2508aq/ar, there is no internal transfer of sound data from the cd signal processing block to dac block. therefore, data can be transferred to dac block through an audio dsp and others. when data is input to dac block without passing through an audio dsp or similar device, data should be connected externally. in that case, emph, lrck, and pcmd can be connected directly with emphi, lrcki, and pcmdi respectively. (see the application circuit.)
?44 cxd2508aq/ar fig. 4-4. input timing for dac block normal-speed playback lrcki (44.1k) bcki (2.12m) 1 24 pcmdi ro lch msb (15) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 rmsb pcmdi lrcki (88.2k) bcki (4.23m) double-speed playback 24 ro lch msb (15) rch msb 234 56789101112 1 2 lo
?45 cxd2508aq/ar 4-4. description of functions no-sound data detection the no-sound data detection function detects low-level data on both the left and right channels in audio data from the 1fs 48-bit slot and outputs a zero detection signal when that data continues unchanged for a certain period of time. the audio data is in two's complement format and data in which the upper 12 bits are all "0" or all "1" is regarded as low level data. when this data continues unchanged for 32,768 samples (743ms when fs = 44.1khz), the zero detection signal is output. in other words, once a certain period of time during which low- level data is detected elapses, the signal is regarded to be in the no-sound state. the zero detection signal is output from zerol (left channel) and zeror (right channel) pins. the zero detection output timing is shown in fig. 4-5. lch rch 32,768th sample of low-level data 32,768th sample of low-level data lrck zeror and zerol lrck zerol zeror lch rch lch rch lch rch lch rch lch low-level data low-level data low-level data low-level data low-level data sound data sound data low-level data low-level data fig. 4-5. zero detection output timing
?46 cxd2508aq/ar forced mute the forced mute can be executed independently for dsp block and dac block. dsp can be forcibly muted by setting "1" in mute for d1 of register a. this mute can be released by setting "0" in mute for d1 of register a. also, the both of left and right channels can be forcibly muted by inputting a high signal to mute pin for dac block (in this event, a soft mute is not performed). in this instance, a fixed pattern is output for the pwm output. to release the mute, input a low signal to mute pin. digital de-emphasis when emphi pin (pin 63) is set high, de-emphasis can be applied by using the iir filter. however, in normal- playback mode the time constants are as follows: t 1 = 50s, t 2 = 15s.
?47 cxd2508aq/ar application circuit scor sbso exck sqso sqck mute sens xrst data xlat clok vss sein cnin dato xlto clko spoa spob spoc xtsl xlon fok mon 37 mdp mds lock test filo fili pco vdo av ss 1 cltv av dd 1 rf bias asyi asyo asye wfck emphi emph dout c4m fstt mnt0 mnt1 mnt3 xrof c2po vss rfck gfs xpck xugf gtop bcki bck pcmdi pcmd lrcki lrck wdck dts3 dts2 rpwm nrpwm avss2 avss3 xta0 xtai av dd 3 av dd 2 lpwm nlpwm v dd dts1 zeror zerol to cpu gnd 2 3 4 5 6 7 8 9 10 1 11 12 13 14 15 16 17 18 19 20 gnd 21 22 23 24 ssp ldon 25 26 27 28 29 30 35 34 31 32 33 gnd dr iver gnd 38 36 40 39 gnd gnd 41 42 43 44 45 46 47 48 49 wdck 50 51 52 53 54 55 56 rfck gfs xpck xugf gtop xrof gnd gnd 57 58 59 60 61 to error rate counter dout 63 64 62 wfck 68 67 65 66 71 73 74 75 zerol zeror 72 76 77 78 79 80 70 69 gnd cxd2508aq rf rf mnt0 mnt1 mnt2 mnt3 gnd ldon fok sens xrst data xlat clk gfs sqso sqck scor mute cout v dd gnd application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?48 cxd2508aq/ar package outline unit: mm cxd2508aq cxd2508aq package structure sony code eiaj code jedec code qfp-80p-l01 * qfp080-p-1420-a package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy 1.6g 23.9 0.4 20.0 ?0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 ?0.1 + 0.15 14.0 ?0.1 + 0.4 17.9 0.4 16.3 0.1 ?0.05 + 0.2 2.75 ?0.15 + 0.35 0.8 0.2 0.15 ?0.05 + 0.1 80pin qfp (plastic) m 0.12 0.15 0?to 10 detail a a sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating 42 alloy m 80pin qfp (plastic) 20.0 ?0.1 + 0.4 24.0 0.3 41 64 65 80 1 24 25 40 0.8 0.35 ?0.1 + 0.15 0.12 14.0 ?0.1 + 0.4 18.0 0.3 0.15 ?0.05 + 0.1 16.6 0.1 ?0.05 + 0.2 0.7 0.1 2.7 0.1 3.1 max 0.15 0?to 10 22.6 qfp-80p-l121 * qfp080-p-1420-ax 1.6g
?49 cxd2508aq/ar cxd2508aq cxd2508ar sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating 42 alloy package structure qfp-80p-l051 * qfp080-p-1420-ah 0.15 0.05 0.24 0.15 2.7 ?0.16 2.94 0.15 0.8 0.15 1.95 0.15 1.45 0?to 10 15 15 15 15 detail a 0.15 23.9 0.2 * 20.0 0.2 0.35 0.1 4 ?1.0 0.8 4 ?0.8 64 41 65 40 80 24 25 m 0.15 1 c1.2 * 14.0 0.2 17.9 0.2 qfp 80pin (plastic) a + 0.20 1.6g note: dimension * ?does not include mold protrusion. sony code eiaj code jedec code package material lead treatment lead material package weight epoxy / phenol resin solder plating 42 alloy package structure 14.0 0.2 * 12.0 0.1 (0.22) 60 41 40 21 20 80 61 1 0.5 0.08 0.18 ?0.03 + 0.08 a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (13.0) 0.1 0.1 0.5 0.2 0?to 10 detail a 80pin lqfp (plastic) 0.5g lqfp-80p-l01 * qfp080-p-1212-a 0.1 note: dimension * ?does not include mold protrusion.

▲Up To Search▲

Price & Availability of SONYCORPORATION-CXD2508AR

	To Download SONYCORPORATION-CXD2508AR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .